Optimizing RISC-V core for machine  learning workloads

dc.contributor.author	Kuchynskyy, Volodymyr
dc.date.accessioned	2024-02-14T08:38:32Z
dc.date.available	2024-02-14T08:38:32Z
dc.date.issued	2022
dc.identifier.citation	Kuchynskyy, Volodymyr. Optimizing RISC-V core for machine learning workloads / Volodymyr Kuchynskyy; Supervisor: Oleg Farenyuk; Ukrainian Catholic University, Department of Computer Sciences. – Lviv: 2022. – 27 p.	uk
dc.identifier.uri	https://er.ucu.edu.ua/handle/1/4393
dc.language.iso	en	uk
dc.title	Optimizing RISC-V core for machine learning workloads	uk
dc.type	Preprint	uk
dc.status	Публікується вперше	uk
dc.description.abstracten	Machine learning has become widely used in many different applications. Specifically, machine learning models on embedded edge systems have been gaining popularity. Due to the high resource requirements of machine learning workloads and highly-constrained embedded systems, the idea of using custom hardware accelerators has become viable. Open-source CPU architectures such as RISC-V could be used for such purposes. Additionally, Field-Programmable Gate Arrays (FPGAs) offer a useful platform for running and prototyping custom hardware. In this thesis, we review the current state of machine learning acceleration hardware, optimize a MobileNetV1 model and describe a design process for prototyping hardware acceleration using CFU playground framework.	uk